A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance, C=.epsilon..epsilon..sub.0 A/d, where .epsilon. is the dielectric constant of the capacitor dielectric, .epsilon..sub.0 is the vacuum permitivity, A is the electrode (or storage node) area and d is the interelectrode spacing. The conditions of DRAM operation such as operating voltage, leakage rate and refresh rate, will in general mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each will maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Nevertheless, in the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. For example, the area allowed for a single cell in a 64-Mbit DRAM is only about 1.4 .mu.m.sup.2. In such limited areas, it is difficult to provide sufficient capacitance using conventional stacked capacitor structures. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include new structures utilizing trench and stacked capacitors, electrodes having textured surface morphology and new capacitor dielectric materials having higher dielectric constants.
As DRAM density has increased (1 MEG and beyond) thin film capacitors, such as stacked capacitors, trenched capacitors, or combinations thereof, have evolved in attempts to meet minimum space requirements. Many of these designs have become elaborate and difficult to fabricate consistently as well as efficiently. Furthermore, the recent generations of DRAMs (4 MEG, 16 MEG for example) have pushed thin film capacitors technology to the limit of processing capability. Thus, greater attention has been given to the development of thin film dielectric materials that possess a dielectric constant significantly greater (&gt;10.times.) than the conventional dielectrics used today, such as silicon oxides or nitrides.
Recently, a lot of attention has been paid to Barium Strontium Titanate (BST), Barium Titanate (BT), Strontium Titanate (ST), Lead Zirconate Titanate (PZT) and other high dielectric constant materials as a cell dielectric material of choice for DRAMs. These materials, in particular BST, have a high dielectric constant (&gt;300) and low leakage currents which makes them very attractive for high density memory devices. However, there are some technical difficulties associated with these materials. One problem with incorporating these materials into present day DRAM cell designs is their chemical reactivity with the polycrystalline silicon (polysilicon or "poly") that conventionally forms the capacitor electrode or a buried electrode contact. Capacitors made by polysilicon-PZT/BST sandwiches undergo chemical and physical degradation with thermal processing. During chemical vapor deposition (CVD) of PZT/BST, oxygen in the ambient tends to oxidize the electrode material. The oxide is undesirable since it has a much lower dielectric constant compared to PZT/BST and adds in series to the capacitance of the PZT/BST, thus drastically lowering the total capacitance of the capacitor. Therefore, even a thin native oxide layer present on the electrode results in a large degradation in capacitance. Furthermore, even when the electrode proper is made of a noble metal, such as Pt, oxygen will still tend to diffuse through it, contaminating the underlying polycrystalline silicon plug.
An approach to the problem is disclosed in U.S. Pat. No. 5,187,638 by G. Sandhu and P. Fazan, herein incorporated by reference, wherein a transition metal, such as Molybdenum, is used as a capacitor plate. A conducting transition metal oxide forms at the interface between the transition metal and the PZT/BST material, thereby forming a barrier layer between the PZT/BST material and Mo electrode.
Another solution to the problem is to introduce a diffusion barrier or barrier layer between the polysilicon plug and an upper portion of the capacitor plate. For example, a triple layer cell plate consisting of poly-Si/Ta/Pt is disclosed in "A STACKED CAPACITOR WITH (BaxSr1-x) TiO3 for 256M DRAM", K. Koyama et al., IEDM 91, pp 823-826, and U.S. Pat. No. 5,053,917, Miyasaka et al. In these references Tantalum, overlaying the silicon, functions as a diffusion barrier, preventing oxygen from migrating into the polysilicon region. In other designs TiN is used as the barrier layer, which unfortunately also tends to oxidize upon further processing. In general, a common problem associated with barrier layers is that they tend to break down during subsequent processing, eventually allowing cross diffusion between the high-.epsilon. material and the underlying electrode or polycrystalline silicon plug. Furthermore, such structures are complex and cumbersome to integrate into a manufacturing process flow.
FIG. 1 schematically illustrates a prior art DRAM having a high-.epsilon. capacitor with a barrier layer susceptible to breakdown. The capacitor structures 18 are generally fabricated in a stacked arrangement disposed over integrated access devices such as MOSFETS and the like. The wafer 20 may for example include field isolation regions 22, active areas 24, word lines 26 and bit lines 28. The capacitor structure is disposed over a buried contact usually comprised of a polysilicon plug 30 making electrical contact between the silicon substrate 20 and capacitor structure 18. The capacitor 18 may comprise an inner electrode 14 such as platinum, deposited over a conductive barrier layer 17 such as tantalum or TiN. A high-.epsilon. dielectric layer 15 is deposited over the inner electrode 14. High-.epsilon. materials proposed for such capacitor structures include BT, ST, BST and PZT. An outer electrode layer 16 is deposited over substantially the entire structure to serve as a common reference electrode. As mentioned earlier, the barrier layer 17 functions as a diffusion barrier for chemical species during processing of the dielectric layer 15 so that the underlying polysilicon plug 30 does not become contaminated or oxidized. For example, silicon atoms from the polysilicon plug may diffuse and oxidize near the electrode surface, where they would create a SiO.sub.2 film having relatively low dielectric constant. However, a common problem in the design and fabrication of such capacitors is the oxidation and partial breakdown of the barrier layer 17 during deposition of dielectric layer 15 or during subsequent thermal processing. Thus, materials and processes must be developed in order to provide simple, cost effective integration of high-.epsilon. materials into high-density DRAM capacitors.